verilator 5.024-1
| Architecture: | x86_64 |
|---|---|
| Repository: | Extra |
| Description: | The fastest free Verilog HDL simulator |
| Upstream URL: | https://www.veripool.org/projects/verilator/wiki/Intro |
| License(s): | LGPL |
| Maintainers: |
Felix Yan Filipe Laíns |
| Package Size: | 5.2 MB |
| Installed Size: | 22.2 MB |
| Last Packager: | Felix Yan |
| Build Date: | 2024-04-10 14:34 UTC |
| Signed By: | Felix Yan |
| Signature Date: | 2024-04-10 14:39 UTC |
| Last Updated: | 2024-04-10 14:41 UTC |