verilator 5.018-1
| Architecture: | x86_64 |
|---|---|
| Repository: | Extra |
| Description: | The fastest free Verilog HDL simulator |
| Upstream URL: | https://www.veripool.org/projects/verilator/wiki/Intro |
| License(s): | LGPL |
| Maintainers: |
Felix Yan Filipe Laíns |
| Package Size: | 5.3 MB |
| Installed Size: | 25.3 MB |
| Last Packager: | Felix Yan |
| Build Date: | 2023-11-02 19:19 UTC |
| Signed By: | Felix Yan |
| Signature Date: | 2023-11-02 19:23 UTC |
| Last Updated: | 2023-11-02 19:25 UTC |