python-pythondata-cpu-vexriscv 2022.08-3 File List

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  • usr/
  • usr/lib/
  • usr/lib/python3.12/
  • usr/lib/python3.12/site-packages/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv-1.0.1.post407-py3.12.egg-info/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv-1.0.1.post407-py3.12.egg-info/PKG-INFO
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv-1.0.1.post407-py3.12.egg-info/SOURCES.txt
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv-1.0.1.post407-py3.12.egg-info/dependency_links.txt
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv-1.0.1.post407-py3.12.egg-info/not-zip-safe
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv-1.0.1.post407-py3.12.egg-info/top_level.txt
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/__init__.py
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/__pycache__/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/__pycache__/__init__.cpython-312.opt-1.pyc
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/__pycache__/__init__.cpython-312.pyc
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/.gitignore
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/.gitmodules
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/Makefile
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/README.md
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv.yaml
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.yaml
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.yaml
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.yaml
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.yaml
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.yaml
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.yaml
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.yaml
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.yaml
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.yaml
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.yaml
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.yaml
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.yaml
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebugHwBP.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebugHwBP.yaml
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.yaml
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.yaml
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebugHwBP.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebugHwBP.yaml
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_Secure.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_Secure.yaml
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_SecureDebug.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/VexRiscv_SecureDebug.yaml
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/build.sbt
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/.gitignore
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/.travis.yml
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/LICENSE
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/README.md
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/assets/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/assets/brieySoc.png
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/build.sbt
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/project/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/project/build.properties
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/project/plugins.sbt
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/Makefile
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/README.md
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/img/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/img/cram-programming-config.png
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/img/iCE40HX8K-breakout-revA.png
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/toplevel.pcf
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board/toplevel.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/Makefile
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/Murax_iCE40_hx8k_breakout_board_xip.pcf
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/README.md
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/img/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/img/cram-programming-config.png
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/iCE40-hx8k_breakout_board_xip/img/iCE40HX8K-breakout-revA.png
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/iCE40HX8K-EVB/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/iCE40HX8K-EVB/Makefile
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/iCE40HX8K-EVB/toplevel.pcf
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/iCE40HX8K-EVB/toplevel.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/scripts/Murax/iCE40HX8K-EVB/toplevel_pll.v
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/c/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/c/murax/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/c/murax/xipBootloader/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/c/murax/xipBootloader/.gitignore
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/c/murax/xipBootloader/crt.S
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/c/murax/xipBootloader/crt.bin
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  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/ressource/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/ressource/hex/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/ressource/hex/muraxDemo.elf
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/ressource/hex/muraxDemo.hex
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/spinal/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/spinal/lib/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/spinal/lib/bus/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/spinal/lib/bus/wishbone/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/spinal/lib/bus/wishbone/Wishbone.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/spinal/lib/eda/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/spinal/lib/eda/icestorm/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/spinal/lib/eda/icestorm/IcestormFlow.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/spinal/lib/misc/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/spinal/lib/misc/HexTools.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/Pipeline.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/Riscv.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/Services.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/Stage.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/TestsWorkspace.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/VexRiscv.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/Briey.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/CustomCsrDemoPlugin.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/CustomInstruction.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/FormalSimple.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenCustomCsr.scala
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  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenDeterministicVex.scala
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  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenFullNoMmu.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenFullNoMmuMaxPerf.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenSmallAndPerformantICache.scala
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  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/Murax.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/MuraxUtiles.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/SimpleBus.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/SynthesisBench.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/ip/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/main/scala/vexriscv/ip/DataCache.scala
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  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/test/scala/vexriscv/experimental/Experiments.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/test/scala/vexriscv/experimental/GenMicro.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/ext/VexRiscv/src/test/scala/vexriscv/experimental/config.scala
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/project/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/project/build.properties
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/project/plugins.sbt
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/src/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/src/main/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/src/main/scala/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/
  • usr/lib/python3.12/site-packages/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala
  • usr/share/
  • usr/share/licenses/
  • usr/share/licenses/python-pythondata-cpu-vexriscv/
  • usr/share/licenses/python-pythondata-cpu-vexriscv/LICENSE
  • usr/src/
  • usr/src/debug/
  • usr/src/debug/python-pythondata-cpu-vexriscv/