verilator 4.212-1
| Architecture: | x86_64 |
|---|---|
| Repository: | Community |
| Description: | The fastest free Verilog HDL simulator |
| Upstream URL: | https://www.veripool.org/projects/verilator/wiki/Intro |
| License(s): | LGPL |
| Maintainers: |
Felix Yan Filipe Laíns |
| Package Size: | 4.6 MB |
| Installed Size: | 22.5 MB |
| Last Packager: | Felix Yan |
| Build Date: | 2021-09-12 02:28 UTC |
| Signed By: | Felix Yan |
| Signature Date: | 2021-09-12 02:30 UTC |
| Last Updated: | 2021-09-12 02:35 UTC |