verilator 4.200-1
| Architecture: | x86_64 |
|---|---|
| Repository: | Community |
| Description: | The fastest free Verilog HDL simulator |
| Upstream URL: | https://www.veripool.org/projects/verilator/wiki/Intro |
| License(s): | LGPL |
| Maintainers: |
Felix Yan Filipe Laíns |
| Package Size: | 4.4 MB |
| Installed Size: | 20.4 MB |
| Last Packager: | Filipe Laíns |
| Build Date: | 2021-04-22 15:12 UTC |
| Signed By: | Filipe Laíns |
| Signature Date: | 2021-04-22 15:15 UTC |
| Last Updated: | 2021-04-22 15:52 UTC |